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integrated circuit systems, inc. ics950220 0467f?07/28/05 block diagram pin configuration recommended application: ck-408 clock for intel ? 845 chipset. output features: 3 - pairs of differential cpu clocks @ 3.3v 3 - 3v66 @ 3.3v 9 - pci @ 3.3v 2 - 48mhz @ 3.3v fixed 1 - 24_48mhz @ 3.3v, 48mhz, 24mhz or 66mhz 1 - ref @ 3.3v, 14.318mhz features/benefits: programmable output frequency. programmable output divider ratios. programmable output rise/fall time. programmable output skew. programmable spread percentage for emi control. watchdog timer technology to reset system if system malfunctions. programmable watch dog safe frequency. support i 2 c index read/write and block read/write operations. uses external 14.318mhz crystal. key specifications: ? cpu output jitter <150ps 3v66 output jitter <250ps cpu output skew <100ps programmable timing control hub? for p4? 1. these outputs have 2x drive strength. * internal pull-up resistor of 120k to vdd ** these inputs have 120k internal pull-down to gnd 48-pin 300-mil ssop power groups vdda = analog core pll vddref = ref, xtal avdd48 = 48mhz 4 s f3 s f2 s f1 s f0 s f k l c u p c z h m 6 6 v 3 z h m k l c i c p z h m 0000 1 0 0 . 0 0 17 6 . 6 63 3 . 3 3 10 00 1 3 3 . 3 3 17 6 . 6 63 3 . 3 3 11110 7 6 . 6 67 6 . 6 64 3 . 3 3 11111 0 0 . 0 0 27 6 . 6 63 3 . 3 3 frequency table for additional frequency selections please refer to byte 0. pll2 pll1 spread spectr um 48mhz_usb pciclk (6:0) 48mhz_dot 3v66_0/24_48mhz# x1 x2 xtal osc cpu divder pci divder wden sel24_48 multsel0 s data sclk vtt_pwrgd# pd# fs (4:0) i ref control logic config. reg. ref 3 7 3 3v66 (3:1) 3v66 /2 divder 3 cpuclkt (2:0) cpuclkc (2:0) reset# vddref x1 x2 gnd *fs0/pciclk7 **fs1/pciclk8 vddpci gnd *wden/pciclk0 pciclk1 pciclk2 pciclk3 vddpci gnd pciclk4 pciclk5 pciclk6 vdd3v66 gnd 3v66_1 3v66_2 3v66_3 #reset vdda 1 1 1 ref/fs2** cpuclkt0 cpuclkc0 vddcpu cpuclkt1 cpuclkc1 gnd vddcpu cpuclkt2 cpuclkc2 multisel0* i ref gnd 48mhz_usb/fs3** 48mhz_dot/sel_24_48* avdd48 gnd 3v66_0/24_48mhz#/fs4** vdd3v66 gnd sclk s data vtt_pwrgd/pd#* gnd 1 ics950220 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 9 20 21 22 23 24 48 47 46 45 44 43 42 41 40 3 9 38 37 36 35 34 33 32 31 30 2 9 28 27 26 25
2 integrated circuit systems, inc. ics950220 0467f?07/28/05 pin description the ics950220 is a single chip clock solution for desktop designs using the intel 845 chipset with pc133 or ddr memory. it provides all necessary clock signals for such a system. the ics950220 is part of a whole new line of ics clock generators and buffers called tch? (timing control hub). this part incorporates ics's newest clock technology which offers more robust features and functionality. employing the use of a serially programmable i 2 c interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. m/n control can configure output frequency with resolution up to 0.1mhz increment. general description r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d , 8 1 , 3 1 , 7 , 1 5 4 , 1 4 , 0 3 d d vr w p. y l p p u s r e w o p v 3 . 3 21 xn i . 2 x m o r f r o t s i s e r k c a b d e e f d n a ) f p 3 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 32 xt u o . ) f p 3 3 ( p a c d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c , 9 2 , 5 2 , 9 1 , 4 1 , 8 , 4 2 4 , 6 3 , 2 3 d n gr w p. y l p p u s v 3 . 3 r o f s n i p d n u o r g 0 2 , 1 2 , 2 2) 1 : 3 ( 6 6 v 3t u o. b u h r o f s t u p t u o k c o l c z h m 6 6 d e x i f v 3 . 3 5 7 k l c i c pt u ot u p t u o k c o l c i c p v 3 . 3 0 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l 6 8 k l c i c pt u o. t u p t u o k c o l c i c p v 3 . 3 1 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l 9 n e d wn i. h g i h d e h c t a l n e h w d e l b a n e . t i u c r i c g o d h c t a w f o e l b a n e e r a w d r a h 0 k l c i c pt u o. t u p t u o k c o l c i c p v 3 . 3 0 1 , 1 1 , 2 1 , 5 1 , 6 1 , 7 1) 1 : 6 ( k l c i c pt u o. s t u p t u o k c o l c i c p v 3 . 3 3 2# t e s e rt u o . t u o e m i t r e m m i t g o d h c t a w r o e u l a v y c n e u q e r f r o f l a n g i s t e s e r m e t s y s e m i t l a e r . w o l e v i t c a s i l a n g i s s i h t 4 2a d d vr w p. v 3 . 3 r e w o p g o l a n a 6 2 d g r w p _ t t vn i ) 0 : 4 ( s f n e h w e n i m r e t e d o t d e s u e b o r t s e v i t i s n e s l e v e l a s i t u p n i l t t v l v 3 . 3 s i h t . ) h g i h e v i t c a ( d e l p m a s e b o t y d a e r e r a d n a d i l a v e r a s t u p n i # d pn i w o l a o t n i e c i v e d e h t n w o d r e w o p o t d e s u n i p t u p n i w o l e v i t c a s u o n o r h c n y s a e r a l a t s y r c e h t d n a o c v e h t d n a d e l b a s i d e r a s k c o l c l a n r e t n i e h t . e t a t s r e w o p . s m 3 n a h t r e t a e r g e b t o n l l i w n w o d r e w o p e h t f o y c n e t a l e h t . d e p p o t s 8 2k l c sn ii r o f n i p k c o l c 2 . t n a r e l o t v 5 y r t i u c r i c c 7 2a t a d so / ii r o f n i p a t a d 2 . t n a r e l o t v 5 y r t i u c r i c c 1 3 # z h m 8 4 _ 4 2 / 0 _ 6 6 v 3t u o h g u o r h t e l b a t c e l e s t u p t u o v 3 . 3i 2 cr o o c v l a n r e t n i m o r f z h m 6 6 e b o t . z h m 4 2 / z h m 8 4 4 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l 3 38 4 d d v ar w p. v 3 . 3 r e w o p g o l a n a 4 3 t o d _ z h m 8 4t u o. t o d r o f t u p t u o k c o l c z h m 8 4 d e x i f v 3 . 3 8 4 _ 4 2 l e sn i . t u p t u o 8 4 _ 4 2 l e s e h t r o f y c n e u q e r f e h t s t c e l e s s i h t . z h m 8 4 = w o l , z h m 4 2 = h g i h 5 3 3 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l b s u _ z h m 8 4t u o. b s u r o f t u p t u o k c o l c z h m 8 4 d e x i f v 3 . 3 7 3f e r it u o s e r i u q e r n i p s i h t . s r i a p k l c u p c e h t r o f t n e r r u c e c n e r e f e r e h t s e h s i l b a t s e n i p s i h t e t a i r p o r p p a e h t h s i l b a t s e o t r e d r o n i d n u o r g o t d e i t r o t s i s e r n o i s i c e r p d e x i f a . t n e r r u c 8 30 l e s t l u mn i s t u p t u o u p c r o f r e i l p i t l u m t n e r r u c e h t g n i t c e l e s r o f t u p n i l t t v l v 3 . 3 6 4 , 3 4 , 9 3) 0 : 2 ( c k l c u p ct u o t n e r r u c e r a e s e h t . s t u p t u o u p c r i a p l a i t n e r e f f i d f o s k c o l c " y r o t n e m e l p m o c " . s a i b e g a t l o v r o f d e r i u q e r e r a s r o t s i s e r l a n r e t x e d n a s t u p t u o 7 4 , 4 4 , 0 4) 0 : 2 ( t k l c u p ct u o d n a s t u p t u o t n e r r u c e r a e s e h t . s t u p t u o u p c r i a p l a i t n e r e f f i d f o s k c o l c " e u r t " . s a i b e g a t l o v r o f d e r i u q e r e r a s r o t s i s e r l a n r e t x e 8 4 2 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l f e rt u o. t u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 , v 3 . 3
3 integrated circuit systems, inc. ics950220 0467f?07/28/05 maximum allowed current n o i t i d n o c n o i t p m u s n o c y l p p u s v 3 . 3 x a m , s d a o l p a c e t e r c s i d x a m v 5 6 4 . 3 = d d v d n g r o d d v = s t u p n i c i t a t s l l a e d o m n w o d r e w o p ) 0 = # n w d r w p ( a m 0 4 e v i t c a l l u f a m 0 6 3 host swing select functions multisel0 board target trace/term z reference r, iref = v dd /(3*rr) output current voh @ z 0 50 ohms rr = 221 1%, iref = 5.00ma ioh = 4* i ref 1.0v @ 50 1 50 ohms rr = 475 1%, iref = 2.32ma ioh = 6* i ref 0.7v @ 50
4 integrated circuit systems, inc. ics950220 0467f?07/28/05 general smbus serial interface information how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
5 integrated circuit systems, inc. ics950220 0467f?07/28/05 byte 0: functionality and frequency select register (default=0) notes: 1. default at power-up will be for latched logic inputs to define frequency, as displayed by bit 3. t i b n o i t p i r c s e d d w p t i b ) 4 : 7 , 2 ( 2 t i b7 t i b6 t i b5 t i b4 t i b k l c u p c z h m 6 6 v 3 z h m k l c i c p z h m % d a e r p s 1 e t o n 4 s f3 s f2 s f1 s f0 s f 00000 0 9 . 0 0 17 2 . 7 63 6 . 3 3d a e r p s r e t n e c % 5 3 . 0 - / + 0000 1 0 0 . 0 0 17 6 . 6 63 3 . 3 3d a e r p s n w o d % 6 . 0 - o t 0 00010 0 0 . 3 0 17 6 . 8 63 3 . 4 3d a e r p s r e t n e c % 5 3 . 0 - / + 00011 0 0 . 5 0 10 0 . 0 70 0 . 5 3d a e r p s r e t n e c % 5 3 . 0 - / + 00 100 0 0 . 7 0 13 3 . 1 77 6 . 5 3d a e r p s r e t n e c % 5 3 . 0 - / + 00 10 1 0 0 . 9 0 17 6 . 2 73 3 . 6 3d a e r p s r e t n e c % 5 3 . 0 - / + 00 110 0 0 . 1 1 10 0 . 4 70 0 . 7 3d a e r p s r e t n e c % 5 3 . 0 - / + 00 111 0 0 . 4 1 10 0 . 6 70 0 . 8 3d a e r p s r e t n e c % 5 3 . 0 - / + 01000 0 0 . 7 1 10 0 . 8 70 0 . 9 3d a e r p s r e t n e c % 5 3 . 0 - / + 01001 0 0 . 0 2 10 0 . 0 80 0 . 0 4d a e r p s r e t n e c % 5 3 . 0 - / + 01010 0 0 . 7 2 17 6 . 4 83 3 . 2 4d a e r p s r e t n e c % 5 3 . 0 - / + 01011 0 0 . 0 3 17 6 . 6 83 3 . 3 4d a e r p s r e t n e c % 5 3 . 0 - / + 01100 3 3 . 3 3 19 8 . 8 84 4 . 4 4d a e r p s r e t n e c % 5 3 . 0 - / + 01101 0 0 . 0 7 17 6 . 6 53 3 . 8 2d a e r p s r e t n e c % 5 3 . 0 - / + 01110 0 0 . 0 8 10 0 . 0 60 0 . 0 3d a e r p s r e t n e c % 5 3 . 0 - / + 01111 0 0 . 0 9 13 3 . 3 67 6 . 1 3d a e r p s r e t n e c % 5 3 . 0 - / + 10 00 0 0 9 . 3 3 15 9 . 6 68 4 . 3 3d a e r p s r e t n e c % 5 3 . 0 - / + 10 00 1 3 3 . 3 3 17 6 . 6 63 3 . 3 3d a e r p s n w o d % 6 . 0 - o t 0 10 0 10 0 0 . 0 2 10 0 . 0 60 0 . 0 3d a e r p s r e t n e c % 5 3 . 0 - / + 10 0 1 1 0 0 . 5 2 10 5 . 2 65 2 . 1 3d a e r p s r e t n e c % 5 3 . 0 - / + 10 10 0 0 9 . 4 3 15 4 . 7 63 7 . 3 3d a e r p s r e t n e c % 5 3 . 0 - / + 10 10 1 0 0 . 7 3 10 5 . 8 65 2 . 4 3d a e r p s r e t n e c % 5 3 . 0 - / + 10 110 0 0 . 9 3 10 5 . 9 65 7 . 4 3d a e r p s r e t n e c % 5 3 . 0 - / + 10 11 1 0 0 . 1 4 10 5 . 0 75 2 . 5 3d a e r p s r e t n e c % 5 3 . 0 - / + 11000 0 0 . 3 4 10 5 . 1 75 7 . 5 3d a e r p s r e t n e c % 5 3 . 0 - / + 1100 1 0 0 . 5 4 10 5 . 2 75 2 . 6 3d a e r p s r e t n e c % 5 3 . 0 - / + 11010 0 0 . 0 5 10 0 . 5 75 . 7 3d a e r p s r e t n e c % 5 3 . 0 - / + 11011 0 0 . 5 5 10 5 . 7 75 7 . 8 3d a e r p s r e t n e c % 5 3 . 0 - / + 11100 0 0 . 0 6 10 0 . 0 80 0 . 0 4d a e r p s r e t n e c % 5 3 . 0 - / + 1110 1 0 0 . 0 7 10 0 . 5 80 5 . 2 4d a e r p s r e t n e c % 5 3 . 0 - / + 11110 7 6 . 6 67 6 . 6 64 3 . 3 3d a e r p s n w o d % 6 . 0 - o t 0 11111 0 0 . 0 0 27 6 . 6 63 3 . 3 3d a e r p s n w o d % 6 . 0 - o t 0 3 t i b s t u p n i d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 4 : 7 , 2 t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 1 t i b l a m r o n - 0 e l b a n e m u r t c e p s d a e r p s - 1 1 0 t i b s t u p n i h c t a l y b d e t c e l e s e b l l i w y c n e u q e r f e f a s g o d h c t a w - 0 ) 0 : 4 ( t i b 0 1 e t y b y b d e m m a r g o r p e b l l i w y c n e u q e r f e f a s g o d h c t a w - 1 0
6 integrated circuit systems, inc. ics950220 0467f?07/28/05 byte 1: output control register (1 = enable, 0 = disable) byte 3: output control register (1 = enable, 0 = disable) byte 2: output control register (1 = enable, 0 = disable) byte 4: output control register (1 = enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b9 3 , 0 41 2 c / t u p c 6 t i b3 4 , 4 41 1 c / t u p c 5 t i b6 4 , 7 41 0 c / t u p c 4 t i b-x k c a b d a e r 4 s f 3 t i b-x k c a b d a e r 3 s f 2 t i b-x k c a b d a e r 2 s f 1 t i b-x k c a b d a e r 1 s f 0 t i b-x k c a b d a e r 0 s f t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 t i b l o r t n o c 6 6 v 3 . c n y s a u p c h t i w s u o n o r h c n y s a z h m 2 3 / 4 6 = i c p / 6 6 v 3 : 0 u p c h t i w s u o n o r h c n y s z h m 3 . 3 3 / 6 . 6 6 = i c p / 6 6 v 3 : 1 6 t i b-x d e v r e s e r 5 t i b-x d e v r e s e r 4 t i b1 31 # z h m 8 4 _ 4 2 / 0 _ 6 6 v 3 3 t i b-x d e v r e s e r 2 t i b2 21 3 _ 6 6 v 3 1 t i b1 21 2 _ 6 6 v 3 0 t i b0 21 1 _ 6 6 v 3 t i b# n i pd w pn o i t p i r c s e d 7 t i b-x ) k c a b d a e r ( l e s t l u m 6 t i b7 11 6 _ k l c i c p 5 t i b6 11 5 _ k l c i c p 4 t i b5 11 4 _ k l c i c p 3 t i b2 11 3 _ k l c i c p 2 t i b1 11 2 _ k l c i c p 1 t i b0 11 1 _ k l c i c p 0 t i b91 0 _ k l c i c p notes: 1. pwd = power on default 2. for disabled clocks, they stop low for single ended clocks. differential cpu clocks stop with cpuclkt at high, cpuclkc off, and external resistor termination will bring cpuclkc low. t i b# n i pd w pn o i t p i r c s e d 7 t i b4 31 t o d _ z h m 8 4 6 t i b5 31 b s u _ z h m 8 4 5 t i b-1 e l b a s i d = 0 , e l b a n e = 1 t c e t e d t f i h s r a e g t e s e r 4 t i b-x d e v r e s e r 3 t i b1 30 , # z h m 8 4 _ 4 2 / 0 _ 6 6 v 3# z h m 8 4 _ 4 2 = 0 , z h m 6 6 . 6 6 = 1 ) t l u a f e d ( 2 t i b-x d e v r e s e r 1 t i b61 8 k l c i c p 0 t i b51 7 k l c i c p
7 integrated circuit systems, inc. ics950220 0467f?07/28/05 byte 7: revision id and device id register byte 8: byte count read back register byte 5: programming edge rate (1 = enable, 0 = disable) byte 6: vendor id register (1 = enable, 0 = disable) t i be m a nd w pn o i t p i r c s e d 7 t i b7 e t y b0 w o h d n a t n u o c e t y b e r u g i f n o c l l i w r e t s i g e r s i h t o t g n i t i r w : e t o n s i t l u a f e d , k c a b d a e r e b l l i w s e t y b y n a m f 0 h . s e t y b 5 1 = 6 t i b6 e t y b0 5 t i b5 e t y b0 4 t i b4 e t y b0 3 t i b3 e t y b1 2 t i b2 e t y b1 1 t i b1 e t y b1 0 t i b0 e t y b1 t i b# n i pd w pn o i t p i r c s e d 7 t i bx1 ) d e v r e s e r ( 6 t i bx1 ) d e v r e s e r ( 5 t i bx1 ) d e v r e s e r ( 4 t i bx1 ) d e v r e s e r ( 3 t i bx1 ) d e v r e s e r ( 2 t i bx1 ) d e v r e s e r ( 1 t i bx1 ) d e v r e s e r ( 0 t i bx1 ) d e v r e s e r ( t i be m a nd w pn o i t p i r c s e d 7 t i b7 d i e c i v e d0 e c i v e d l a u d i v i d n i n o d e s a b e b l l i w s e u l a v d i e c i v e d . e s a c s i h t n i " h 2 2 " 6 t i b6 d i e c i v e d0 5 t i b5 d i e c i v e d1 4 t i b4 d i e c i v e d0 3 t i b3 d i e c i v e d0 2 t i b2 d i e c i v e d0 1 t i b1 d i e c i v e d1 0 t i b0 d i e c i v e d0 t i be m a nd w pn o i t p i r c s e d 7 t i b3 t i b d i n o i s i v e rx n o i s i v e r s ' e c i v e d l a u d i v i d n i n o d e s a b e b l l i w s e u l a v d i n o i s i v e r 6 t i b2 t i b d i n o i s i v e rx 5 t i b1 t i b d i n o i s i v e rx 4 t i b0 t i b d i n o i s i v e rx 3 t i b3 t i b d i r o d n e v0) d e v r e s e r ( 2 t i b2 t i b d i r o d n e v0) d e v r e s e r ( 1 t i b1 t i b d i r o d n e v0) d e v r e s e r ( 0 t i b0 t i b d i r o d n e v1) d e v r e s e r (
8 integrated circuit systems, inc. ics950220 0467f?07/28/05 byte 10: programming enable bit 8 watchdog control register byte 11: vco frequency m divider (reference divider) control register byte 12: vco frequency n divider (vco divider) control register byte 9: watchdog timer count register t i be m a nd w pn o i t p i r c s e d 7 t i b7 d w0 ? x o t d n o p s e r r o c s t i b 8 e s e h t f o n o i t a t n e s e r p e r l a m i c e d e h t e d o m m r a l a o t s e o g t i e r o f e b t i a w l l i w r e m i t g o d h c t a w e h t s m 0 9 2 s i p u r e w o p t a t l u a f e d . g n i t t e s e f a s e h t o t y c n e u q e r f e h t t e s e r d n a . s d n o c e s 3 . 2 = s m 0 9 2 ? 8 6 t i b6 d w0 5 t i b5 d w0 4 t i b4 d w0 3 t i b3 d w1 2 t i b2 d w0 1 t i b1 d w0 0 t i b0 d w0 t i be m a nd w pn o i t p i r c s e d 7 t i b8 v i d nx 8 t i b r e d i v i d n 6 t i b6 v i d mx e h t o t d s o p s e r r o c ) 0 : 6 ( v i d m f o n o i t a t n e s e r p s e r l a m i c e d e h t e h t o t l a u q e s i p u r e w o p t a t l u a f e d . e u l a v r e d i v i d e c n e r e f e r . n o i t c e l e s s t u p n i d e h c t a l 5 t i b5 v i d mx 4 t i b4 v i d mx 3 t i b3 v i d mx 2 t i b2 v i d mx 1 t i b1 v i d mx 0 t i b0 v i d mx t i be m a nd w pn o i t p i r c s e d 7 t i b7 v i d nx e h t o t d n o p s e r r o c ) 0 : 8 ( v i d n f o n o i t a t n e s e r p e r l a m i c e d e h t e h t o t l a u q e s i p u r e w o p t a t l u a f e d . e u l a v r e d i v i d o c v . 1 1 e t y b n i d e t a c o l s i 8 v i d n e c i t o n . n o t c e l e s s t u p n i d e h c t a l 6 t i b6 v i d nx 5 t i b5 v i d nx 4 t i b4 v i d nx 3 t i b3 v i d nx 2 t i b2 v i d nx 1 t i b1 v i d nx 0 t i b0 v i d nx t i be m a nd w pn o i t p i r c s e d 7 t i b m a r g o r p e l b a n e 0 t i b e l b a n e g n i m m a r g o r p 1 0 e t y b r o s e h c t a l w h y b d e t c e l e s e r a s e i c n e u q e r f . g n i m m a r g o r p o n = 0 i l l a e l b a n e = 2 . g n i m a r g o r p c 6 t i be l b a n e d w1 . t i b e l b a n e g o d h c t a w . e l b a n e = 1 , e l b a s i d = 0 . e u l a v d e h c t a l n e d w e t i r w r e v o l l i w t i b s i h t 5 t i bm r a l a d w1 s u t a t s m r a l a = 1 l a m r o n = 0 s u t a t s m r a l a g o d h c t a w 4 t i b4 f s0 e f a s e h t e r u g i f n o c l l i w s t i b e s e h t o t g n i t i r w . s t i b y c n e u q e r f e f a s g o d h c t a w e l b a t 4 : 7 , 2 t i b 0 e t y b o t g n i d n o p s r r o c y c n e u q e r f 3 t i b3 f s0 2 t i b2 f s0 1 t i b1 f s0 0 t i b0 f s0
9 integrated circuit systems, inc. ics950220 0467f?07/28/05 byte 14: spread spectrum control register byte 13: spread spectrum control register t i be m a nd w pn o i t p i r c s e d 7 t i b7 s sx d a e r p s e h t m a r g o r p l l i w t i b ) 0 : 2 1 ( m u r t c e p s d a e r p s e h t e h t n o d e s a b d e t a l u c l a c e b o t s d e e n t n e c e r p d a e r p s . e g a t n e c e r p d a e r p s d n a t n u o m a g n i d a e r p s , e l i f o r p g n i d a e r p s , y c n e u q e r f o c v d a e r p s r o f e r a w t f o s s c i e s u o t d e d n e m m o c e r s i t i . y c n e u q e r f . r e d i v i d s f d e h c t a l s i n o r e w o p t l u a f e d . g n i m m a r g o r p 6 t i b6 s sx 5 t i b5 s sx 4 t i b4 s sx 3 t i b3 s sx 2 t i b2 s sx 1 t i b1 s sx 0 t i b0 s sx t i be m a nd w pn o i t p i r c s e d 7 t i bd e v r e s e rxd e v r e s e r 6 t i bd e v r e s e rxd e v r e s e r 5 t i bd e v r e s e rxd e v r e s e r 4 t i b2 1 s sx 2 1 t i b m u r t c e p s d a e r p s 3 t i b1 1 s sx 1 1 t i b m u r t c e p s d a e r p s 2 t i b0 1 s sx 0 1 t i b m u r t c e p s d a e r p s 1 t i b9 s sx 9 t i b m u r t c e p s d a e r p s 0 t i b8 s sx 8 t i b m u r t c e p s d a e r p s byte 15: output divider control register byte 16: output divider control register t i be m a nd w pn o i t p i r c s e d 7 t i b3 v i d u p c0 4 e s e h t a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c 2 u p c o t r e f e r e l b a t n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i s t i b . r e d i v i d s f d e h c t a l s i p u r e w o p t a t l u a f e d . 1 e l b a t 6 t i b2 v i d u p c1 5 t i b1 v i d u p c0 4 t i b0 v i d u p c0 3 t i b3 v i d u p c0 a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c ) 0 : 1 ( u p c r e f e r e l b a t n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i s t i b 4 e s e h t . r e d i v i d s f d e h c t a l s i p u r e w o p t a t l u a f e d . 1 e l b a t o t 2 t i b2 v i d u p c1 1 t i b1 v i d u p c0 0 t i b0 v i d u p c0 t i be m a nd w pn o i t p i r c s e d 7 t i b3 v i d0 e s e h t a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c 0 _ 6 6 v 3 o t r e f e r e l b a t n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i s t i b 4 . r e d i v i d s f d e h c t a l s i p u r e w o p t a t l u a f e d . 1 e l b a t 6 t i b2 v i d1 5 t i b1 v i d0 4 t i b0 v i d1 3 t i b3 v i d0 a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c ) 1 : 3 ( 6 6 v 3 r e f e r e l b a t n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i s t i b 4 e s e h t . r e d i v i d s f d e h c t a l s i p u r e w o p t a t l u a f e d . 1 e l b a t o t 2 t i b2 v i d1 1 t i b1 v i d0 0 t i b0 v i d1
10 integrated circuit systems, inc. ics950220 0467f?07/28/05 byte 17: output divider control register byte 18: group skew control register byte 19: group skew control register table 1 table 2 ) 2 : 3 ( v i d 0 01 00 11 1 ) 0 : 1 ( v i d 0 02 /4 /8 /6 1 / 1 03 /6 /2 1 /4 2 / 0 15 /0 1 /0 2 /0 4 / 1 17 /4 1 /8 2 /6 5 / ) 2 : 3 ( v i d 0 01 00 11 1 ) 0 : 1 ( v i d 0 04 /8 /6 1 /2 3 / 1 03 /6 /2 1 /4 2 / 0 15 /0 1 /0 2 /0 4 / 1 19 /8 1 /6 3 /2 7 / t i be m a nd w pn o i t p i r c s e d 7 t i b1 w e k s _ 6 6 v 30 k l c u p c o t t c e p s e r h t i w ) 1 : 3 ( 6 6 v 3 e h t y a l e d s t i b 2 e s e h t s p 0 5 7 = 1 1 s p 0 0 5 = 0 1 s p 0 5 2 = 1 0 s p 0 = 0 0 6 t i b0 w e k s _ 6 6 v 30 5 t i bd e v r e s e r0d e v r e s e r 4 t i bd e v r e s e r0d e v r e s e r 3 t i b1 w e k s _ 6 6 v 30 k l c u p c o t t c e p s e r h t i w 0 _ 6 6 v 3 e h t y a l e d s t i b 2 e s e h t s p 0 5 7 = 1 1 s p 0 0 5 = 0 1 s p 0 5 2 = 1 0 s p 0 = 0 0 2 t i b0 w e k s _ 6 6 v 30 1 t i bd e v r e s e r0d e v r e s e r 0 t i bd e v r e s e r0d e v r e s e r t i be m a nd w pn o i t p i r c s e d 7 t i b1 w e k s _ u p c0 o t t c e p s e r h t i w 2 t / c k l c u p c e h t y a l e d s t i b 2 e s e h t ) 0 : 1 ( t / c k l c u p c s p 0 5 7 = 1 1 s p 0 0 5 = 0 1 s p 0 5 2 = 1 0 s p 0 = 0 0 6 t i b0 w e k s _ u p c0 5 t i bd e v r e s e r0d e v r e s e r 4 t i bd e v r e s e r0d e v r e s e r 3 t i b1 w e k s _ u p c0 e h t y a l e d s t i b 2 e s e h t) 0 : 1 ( t / c k l c u p co t t c e p s e r h t i w k c o l c 2 t / c k l c u p c s p 0 5 2 = 1 0 s p 0 = 0 0s p 0 5 7 = 1 1 s p 0 0 5 = 0 1 2 t i b0 w e k s _ u p c0 1 t i bd e v r e s e r0d e v r e s e r 0 t i bd e v r e s e r0d e v r e s e r t i be m a nd w pn o i t p i r c s e d 7 t i bv n i _ 6 6 v 30 t i b n o i s r e v n i e s a h p 0 _ 6 6 v 3 6 t i bv n i _ 6 6 v 30 t i b n o i s r e v n i e s a h p ) 1 : 3 ( 6 6 v 3 5 t i bv n i _ u p c0 t i b n o i s r e v n i e s a h p 2 u p c 4 t i bv n i _ u p c0 t i b n o i s r e v n i e s a h p ) 0 : 1 ( u p c 3 t i b 3 v i d i c p1 s t i b 4 e s e h t a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c i c p . 2 e l b a t o t r e f e r e l b a t n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i . r e d i v i d s f d e h c t a l s i p u r e w o p t a t l u a f e d 2 t i b 2 v i d i c p0 1 t i b 1 v i d i c p0 0 t i b 0 v i d i c p1
11 integrated circuit systems, inc. ics950220 0467f?07/28/05 byte 20: group skew control register byte 21: slew rate control register byte 22: slew rate control register byte 23: slew rate control register t i be m a nd w pn o i t p i r c s e d 7 t i b3 w e k s _ i c p1 s n 3 . 0 - m o r f w e k s ) 0 : 6 ( i c p o t u p c e h t e g n a h c n a c s t i b 4 e s e h t r o t n e m e r c n i y r a n i b h c a e . s n 5 . 0 s i p u r e w o p t a t l u a f e d . s n 2 . 1 e h t f o y a l e d e h t e s a e r c e d r o e s a e r c n i l l i w ) 0 : 3 ( s t i b f o t n e m e r c e d . s p 0 0 1 y b s k c o l c i c p 6 t i b2 w e k s _ i c p0 5 t i b1 w e k s _ i c p0 4 t i b0 w e k s _ i c p0 3 t i b3 w e k s _ i c p1 s n 6 . 0 - m o r f w e k s ) 7 : 8 ( i c p o t u p c e h t e g n a h c n a c s t i b 4 e s e h t r o t n e m e r c n i y r a n i b h c a e . s n 4 . 0 s i p u r e w o p t a t l u a f e d . s n 2 . 1 e h t f o y a l e d e h t e s a e r c e d r o e s a e r c n i l l i w ) 0 : 3 ( t i b f o t n e m e r c e d . s p 0 0 1 y b s k c o l c i c p 2 t i b2 w e k s _ i c p0 1 t i b1 w e k s _ i c p0 0 t i b0 w e k s _ i c p0 t i be m a nd w pn o i t p i r c s e d 7 t i b1 w e l s f e r1 . s t i b l o r t n o c e t a r w e l s k c o l c f e r k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 6 t i b0 w e l s f e r0 5 t i b1 w e l s ) 4 : 6 ( i c p1 . s t i b l o r t n o c e t a r w e l s k c o l c ) 4 : 6 ( i c p k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 4 t i b0 w e l s ) 4 : 6 ( i c p0 3 t i b ) 1 : 3 ( i c p1 w e l s 1 . s t i b l o r t n o c e t a r w e l s k c o l c ) 1 : 3 ( i c p k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 2 t i b ) 1 : 3 ( i c p0 w e l s 0 1 t i b 0 i c p1 w e l s 1 . s t i b l o r t n o c e t a r w e l s k c o l c 0 i c p k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 0 t i b 0 i c p0 w e l s 0 t i be m a nd w pn o i t p i r c s e d 7 t i bd e v r e s e rx d e v r e s e r 6 t i bd e v r e s e rx 5 t i b1 w e l s h c v1 . s t i b l o r t n o c e t a r w e l s k c o l c h c v k k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 4 t i b0 w e l s h c v0 3 t i b1 w e l s b s u 8 41 . s t i b l o r t n o c e t a r w e l s k c o l c b s u 8 4 k k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 2 t i b0 w e l s b s u 8 40 1 t i b1 w e l s t o d 8 41 . s t i b l o r t n o c e t a r w e l s k c o l c t o d 8 4 k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 0 t i b0 w e l s t o d 8 40 t i be m a nd w pn o i t p i r c s e d 7 t i bd e v r e s e r1d e v r e s e r 6 t i bd e v r e s e r0 d e v r e s e r 5 t i b1 w e l s f i c p1 . s t i b l o r t n o c e t a r w e l s k c o l c ) 0 : 1 ( f i c p k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 4 t i b0 w e l s f i c p0 3 t i b1 w e l s _ ) 1 : 3 ( 6 6 v 31 . s t i b l o r t n o c e t a r w e l s k c o l c ) 1 : 3 ( 6 6 v 3 k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 2 t i b1 w e l s _ ) 1 : 3 ( 6 6 v 30 1 t i b1 w e l s _ 0 _ 6 6 v 31 . s t i b l o r t n o c e t a r w e l s k c o l c 0 _ 6 6 v 3 k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 0 t i b0 w e l s _ 0 _ 6 6 v 30
12 integrated circuit systems, inc. ics950220 0467f?07/28/05 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c case temperature . . . . . . . . . . . . . . . . . . . . . . . . 115c storage temperature . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units input high voltage v ih 2 v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v input high current i ih v in = v dd -5 5 ma i il1 v in = 0 v; inputs with no pull-up resistors -5 ma i il2 v in = 0 v; inputs with pull-up resistors -200 operating supply current i dd3.3op c l = full load 229 221 360 ma powerdown current i dd3.3pd iref=2.32 ma 21 25 ma input frequency f i v dd = 3.3 v 14.318 mhz pin inductance l pin 7nh c in logic inputs 5 pf c out output pin capacitance 6 pf c inx x1 & x2 pins 27 45 pf transition time 1 t trans to 1st crossing of target frequency 3 ms settling time 1 t s from 1st crossing to 1% target fre q uenc y 3ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target fre q uenc y 3ms t pzh ,t pzl output enable delay (all outputs) 1 10 ns t phz ,t plz output disable delay (all outputs) 1 10 ns 3v66 to pci s 3v66-pci 3v66 (5:0) leads 33mhz pci 1.5 2.12 3.5 ns 1 guaranteed by design, not 100% tested in production. delay 1 input capacitance 1 input low current
13 integrated circuit systems, inc. ics950220 0467f?07/28/05 electrical characteristics - cpu 0.7v current mode differential pair t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf parameter symbol conditions min typ max units notes current source output impedance zo 1 v o = v x 3000 ? 1 voltage high vhigh 660 770 850 1 voltage low vlow -150 5 150 1 max volta g e vovs 756 1150 1 min volta g e vuds -300 -7 1 crossin g volta g e (abs) vcross(abs) 250 350 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all ed g es 12 140 mv 1 lon g accurac y ppm see tperiod min-max values -300 300 ppm 1,2 200mhz nominal 4.9985 5.0015 ns 2 200mhz spread 4.9985 5.0266 ns 2 166.66mhz nominal 5.9982 6.0018 ns 2 166.66mhz spread 5.9982 6.0320 ns 2 133.33mhz nominal 7.4978 7.5023 ns 2 133.33mhz spread 7.4978 5.4000 ns 2 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz spread 9.9970 10.0533 ns 2 200mhz nominal 4.8735 ns 1,2 166.66mhz nominal/spread 5.8732 ns 1,2 133.33mhz nominal/spread 7.3728 ns 1,2 100.00mhz nominal/spread 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 332 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 344 700 ps 1 rise time variation d-t r 30 125 ps 1 fall time variation d-t f 30 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 49 55 % 1 skew t sk3 v t = 50% 8 100 ps 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 60 150 ps 1 1 guaranteed b y desi g n, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref output is at 14.31818mhz tperiod average period absolute min period t absmin statistical measurement on single ended signal using oscilloscope math function. mv measurement on single ended si g nal usin g absolute value. mv
14 integrated circuit systems, inc. ics950220 0467f?07/28/05 electrical characteristics - pciclk t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 33.33 mhz output impedance r dsp1 1 v o = v dd *(0.5) 12 55 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.55 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -33 -33 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 188 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.79 2 ns duty cycle d t1 1 v t = 1.5 v 45 52 55 % skew t sk1 1 v t = 1.5 v 280 500 ps jitter,cycle to cyc t j c y c-c y c 1 v t = 1.5 v 200 500 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - 3v66 t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 mhz output impedance r dsp1 1 v o = v dd *(0.5) 12 33 55 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.55 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -33 -33 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.55 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.32 2 ns duty cycle d t1 1 v t = 1.5 v 45 51.7 55 % skew t sk1 1 v t = 1.5 v 16 250 ps jitter t j c y c-c y c 1 v t = 1.5 v 200 250 ps 1 guaranteed by design, not 100% tested in production. note: 3v66@66mhz- main pll
15 integrated circuit systems, inc. ics950220 0467f?07/28/05 electrical characteristics - vch, 48mhz dot, 48mhz, usb t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 v o = v dd *(0.5) 48 mhz output impedance r dsp1 1 v o = v dd *(0.5) 12 55 ? output high voltage v oh 1 i oh = -1 ma 2.4 3.1 v output low voltage v ol 1 i ol = 1 ma 0.19 0.55 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -29 -23 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma 48dot rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 0.77 1 ns 48dot fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 0.84 1 ns vch 48 usb rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 11.12 2 ns vch 48 usb fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 11.42 2 ns 48dotduty cycle d t1 1 v t = 1.5 v 45 49.9 55 % 48 usb duty cycle d t1 1 v t = 1.5 v 45 54.9 55 % jitter t j c y c-c y c 1 v t = 1.5 v 131 350 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - ref t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 14.31 mhz output impedance r dsp1 1 v o = v dd *(0.5) 20 60 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.4 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -29 -23 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 11.7 2ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 11.76 2 ns duty cycle d t1 1 v t = 1.5 v 45 53.5 55 % jitter t j c y c-c y c 1 v t = 1.5 v 305 1000 ps 1 guaranteed by design, not 100% tested in production.
16 integrated circuit systems, inc. ics950220 0467f?07/28/05 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
17 integrated circuit systems, inc. ics950220 0467f?07/28/05 all 3v66 clocks are to be in pphase with each other. in the case where 3v66_1 is configured as 48mhz vch clock, there is no defined phase relationship between 3v66_1/vch and other 3v66 clocks. the pci group should lag 3v66 by the standard skew described below as tpci. 3v66 & pci phase relationship 3v66 (1:0) 3v66 (4:2) 3v66_5 pciclk_f (2:0) pciclk (6:0) tpci group skews at common transition edges group symbol conditions min typ max units 3v66 3v66 3v66 (5:0) pin to pin skew 0 500 ps pci pci pci_f (2:0) and pci (6:0) pin to pin skew 0 500 ps 3v66 to pci s 3v66-pci 3v66 (5:0) leads 33mhz pci 1.5 3.5 ns 1 guaranteed by design, not 100% tested in production. pd# functionality # p o t s _ u p ct u p cc u p c6 6 v 3t u o _ z h m 6 6 f _ k l c i c p k l c i c p k l c i c p t o d / b s u z h m 8 4 1l a m r o nl a m r o nz h m 6 6n i _ z h m 6 6n i _ z h m 6 6n i _ z h m 6 6z h m 8 4 0t l u m * f e r it a o l fw o lw o lw o lw o lw o l
18 integrated circuit systems, inc. ics950220 0467f?07/28/05 the impact of asserting the pci_stop# signal will be the following. all pci[6:0] and stoppable pci_f[2,0] clocks will latch low in their next high to low transition. the pci_stop# setup time tsu is 10 ns, for transitions to be recognized by the next risin g edge. pci_stop# pci_f[2:0] 33mhz pci[6:0] 33mhz tsu assertion of pci_stop# waveforms pci_stop# - assertion (transition from logic "1" to logic "0") cpu_stop# cput cpuc the impact of asserting the cpu_stop# pin is all cpu outputs that are set in the i 2 c configuration to be stoppable via assertion of cpu_stop# are to be stopped after their next transition following the two cpu clock edge sampling as shown. the final state of the stopped cpu signals is cput=high and cpuc=low. there is to be no change to the output drive current values. the cput will be driven high with a current value equal to (multsel0) x (i ref), the cpuc signal will not be driven. cpu_stop# - assertion (transition from logic "1" to logic "0") assertion of cpu_stop# waveforms cpu_stop# functionality # p o t s _ u p ct u p cc u p c 1l a m r o nl a m r o n 0t l u m * f e r it a o l f
19 integrated circuit systems, inc. ics950220 0467f?07/28/05 index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l 300 mil ssop package min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 min max min max 48 15.75 16.00 .620 .630 10-0034 symbol in millimeters in inches common dimensions common dimensions see variations see variations 0.635 basic 0.025 basic reference doc.: jedec publication 95, mo-118 variations see variations see variations n d mm. d (inch) ordering information ics950220 y flft example: ics xxxx y f lf - t designation for tape and reel packaging rohs compliant (optional) package type f = ssop revision designator (will not correlate with datasheet revision) device type prefix ics, av = standard device
20 integrated circuit systems, inc. ics950220 0467f?07/28/05 revision history rev. issue date description page # f 7/28/2005 added lf ordering information. 19

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